The present disclosure relates in general to semiconductor memory devices.
The physical dimensions of a feature on a chip are referred to as “feature size.” Reducing or scaling the feature size on a chip permits more components to be fabricated on each chip, and more components to be fabricated on each wafer, thereby reducing manufacturing costs on a per-wafer and per-chip basis. Memory devices are included in the devices that undergo such scaling to reduce manufacturing costs. In addition to this scaling, layout changes are done to increase the packing density to also allow more components to be fabricated on each wafer. Likewise, other goals that can be accomplished through changes to the layout include facilitating production and improving device performance. However, these layout changes can lead to various performance issues, including speed, noise, or stability challenges, within the memory cell or memory cell arrays.
The challenges in a layout of a dual ported memory cell are especially great. Dual port memory cells are important in that they enable simultaneous accesses from two ports, versus a signal port memory cell in which data reads and writes are performed via a single port. Despite these benefits however, additional challenges are present in dual port cells. For example, the size of a dual port SRAM can often be at least twice the size of a single port SRAM using the same design rules. Therefore, more aggressive layouts are often needed to improve the cost effectiveness, often resulting in further challenges to the cells' performance.
Accordingly, what is needed in the art are memory device layouts that give performance and/or cost improvements.